Principal Signal Processing/HDL Modeling Engineer
Kforce Inc.

Job Info

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RESPONSIBILITIES:

Kforce has a client in San Diego, California (CA) is seeking to hire a hybrid/remote Principal Signal Processing/HDL Modeling Engineer. A Modeling Engineer is a member of the development of digital signal processing related VHDL for use in communication datalink systems and other programs as required.Responsibilities include:

• Principal Signal Processing/HDL Modeling Engineer will develop algorithms
• Develops MATLAB fixed-point, bit-accurate modeling for communication datalinks
• Able to breakdown an FPGA system into sub-components and create input/output vectors for discrete VHDL verification
• Provide architectural and detailed DSP designs, including modulation/demodulation, and frequency, phase, time, and AGC tracking loops
• Provides technical direction and strategy to engineering development efforts for solving complex issues
• Principal Signal Processing/HDL Modeling Engineer outlines and communicates the most appropriate technical approach for business development activities
• Plans and evaluates architectural design and reviews system performance
• Identifies, investigates, resolves technical issues, and mitigate risks
• Participate in engineering design change boards and technical/project reviews
• Develops MATLAB fixed-point, bit-accurate modeling for communication datalinks
• Principal Signal Processing/HDL Modeling Engineer can breakdown an FPGA system into sub-components and create input/output vectors for discrete VHDL verification
• Provide architectural and detailed DSP designs, including modulation/demodulation, and frequency, phase, time, and AGC tracking loops
• Principal Signal Processing/HDL Modeling Engineer performs complex electrical engineering duties following designated standards and procedures
• Works closely with engineering disciplines; Duties require application of engineering principles and techniques

REQUIREMENTS:

• Bachelor's degree in Electronic Engineering, Computer Engineering, or Science discipline; Master's degree preferred
• 10-12+ years of experience of Signal Processing/HDL Modeling
• Previous work experience in VHDL design mandatory
• Familiar with networking architectures and multiple access techniques
• Familiar with VHDL or Verilog design and FPGA architectures
• Experience with FPGA implementation of DSP functions
• Experience in Algorithm Development
• Experience in designing, developing, and testing RTL
• Effective written and oral communication skills
• Ability to use typical office automation products such as word processors and spreadsheets
• Knowledge of customer needs and competing products
• Mental ability to perform analytical work
• Applies fundamental engineering principles, procedures, and techniques to performs advanced systems engineering assignments related to the development of electronic and software intensive systems and subsystems
• Familiar with VHDL or Verilog design and FPGA architectures
• Strong leadership and control of the work process from beginning to end is necessary
• Applies advanced systems methods, theories, and research techniques
• Ability to prioritize work, complete multiple tasks, and work under deadlines
• Knowledge of FPGA design environments, including ISE, Vivado, EDK, Modalism, and MATLAB is a plus

Kforce is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, pregnancy, sexual orientation, gender identity, national origin, age, protected veteran status, or disability status.

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