Experience range : 8+ year
* Senior DFT engineer with good knowledge on ATPG, JTAG and MBIST.
* ATPG pattern generation and test coverage debug using Mentor ATPG tools.
* Scan and OCC chain insertion using Design Compiler.
* RTL and gate level DFT verifications for DFT logic.
Any special or skills related notes:
* Hands on experience with Scan (Design Compiler tool) Scan and ATPG (Mentor - Tessent Tool)
* Good knowledge on MBIST and JTAG
* iJTAG and IEEE1500 wrapper understanding.
Education: Bachelor's degree in Engineering
Actual compensation offer to candidate may vary from posted hiring range based upon geographic location, work experience, education, and/or skill level. The pay ratio between base pay and target incentive (if applicable) will be finalized at offer.
Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status. (Arrow EEO/AAP policy)